Because the inputs to the 4 flip-flops are shared between Fetch and Store operations, I wonder if I need to design some kind of multiplexer to choose which part need to be connected to the flip-flops when Fetch or Store is triggered. If that is true, what kind of multiplexer would only work on the falling edge of the clock?
No multiplexor is needed. What I recommend is that the inputs to each of the flip-flops be an Or of the fetch data and the store data. The fetch data should be an And of the Fetch signal with one of the D1-D4 data. Likewise, the store data should be an And of the Store signal with one of the C1-C4 data.
How do we mimick the falling edge of the clock to trigger out flip flop? I can set either Fetch or Store as 1 at the start, but the flip flop stores when the clock input falls to 0. Do I need to preset the clock input as a 1 by placing a not gate there? Then a fetch or store would change it to a 0, setting the state. Would that be sufficient?
You should connect the Fetch Wire to the common of a SPDTSwitch with its connect0 Wire hooked up to the low of a Battery and its connect1 Wire hooked up to the hight of the Battery. Then when you flip the switch from 0 to 1 and then back to 0, you will get a falling edge on the Fetch Wire as input for the clock input of your flip-flop. Likewise for the Store Wire.
I was just wondering, when you say that the 4 flip-flops store the results of the 7 M input switches and the other 4 C input switches, can I just draw both the inputs into the same 4 flip-flops, which will be decided by the fetch and store switches? Or do I have to draw another 4 flip-flops for the other inputs?
You should only have 4 black-box flip-flops (draw the inside of the flip-flop elsewhere). You cannot just connect both results directly to the flip-flops. You have to use logic gates like And or Or gates to combine them appropriately.
Another question concerning flip flops. I'm confused as to what the book says and what the websites say when they refer to flip flops. You say not to use a D-Latch. But the the D-Latch on the website looks like the D Flip flop in the book. Is the book version also not to be used? Also, the book doesn't utilize the clock in the flip-flop circuit diagram. Should we just ignore all the diagrams in the book and just use the flip flops on the website?
Yes, use the flip-flop from the website. The book, like many others does not distinguish between a latch and a flip-flop.
Okay, I have an idea right now that I use the M1 to M7 switches to use as the inputs for a parity checker. Which will take the inputs of 4 of the M1 to M7 inputs, and XORing them together to check for even parity. Now what I'm stuck on is when I get one of the parity bits to produce an error. How can I find the exact bit that needs to be corrected. Also how does the C1 to C4 switches get involved with the circuit diagram itself? I'm not too sure about it?
This is where the Hamming Code applies. After the XOR, you can get anywhere from 0 to 3 parity errors. If there are no parity errors, then bits M3, M5, M6 and M7 give you the values for D1, D2, D3, and D4 respectively. If there are any parity errors, then which of the M1-M7 has an error is determined by which of the parity bits had an error (that is odd parity when it should be even parity). For example, if all of the parity bits were in error, then M7 would have to be in error because that's the only M that contributes to all three parity bits (M1, M2, and M4). Similarly, if only parity bit M1 was in error, then M1 must be the error bit since M1 is the only M bit that contributes only to M1. You should create a Karnaugh Map for D1 that has inputs M3, ParityErrorM1, ParityErrorM2, and ParityErrorM4. Most of the time, the value of D1 is exactly the same as the value of M3 except when ParityErrorM1 and ParityErrorM2 are both 1 and ParityErrorM4 is 0, in which case, the value of D1 is the opposite of the value of M3. Repeat for D2, D3, and D4.
The C1 to C4 inputs come from the CPU and give the values for E3, E5, E6, and E7 respectively, E1, E2, and E4 are parity bits computed from combinations of the C1-C4 inputs as specified by the Hamming Code.
i dont really understand the functions of the fetch and store spdt switches. could you please explain them to me. also, for the 7 spdt switches M1 to M7, why do i need them? cant i just feed the 4 data bits into the circuit and store the results into the wires E1 to E7? sorry, these might sound silly to you but im a little confused.
The Fetch and Store SPDTSwitches simulate control lines from the CPU to the memory controller. When the CPU wants to store a new value in the ECC memory, it will put it's data on C1 to C4, then cycle the Store control signal from 0 to 1 and back to 0. When the CPU wants to retrieve its data from memory, it will cycle the Fetch control signal from 0 to 1 and back to 0. The SPDTSwitches for Fetch and Store both have connect0 connected to the low of a Battery and connect1 connected to the high of the Battery. The common for the Fetch SPDTSwitch is connected to Wire Fetch and likewise the common for the Store SPDTSwitch is connected to the Wire Store. This allows the user of your program to pretend to be the CPU and cycle the Fetch Wire by entering switch position 0, then 1, then 0 again for the Fetch SPDTSwitch. The purpose of the Store and Fetch signals is to serve as the clock input for your four flip-flops (see the question below). When either the Store or Fetch signals transitions from 1 to 0, then the flip-flops will remember the current value and maintain that value until the next transition. The reason why you need the flip-flops is so that the "bus" (which we don't actually implement in this assignment) can run faster. If the memory controller grabs the data from C1 to C4 exactly when the Store signal transitions from 1 to 0, then right after that, the bus can be used for something else without having to wait for the memory controller to compute the right values for E1 to E7. Likewise, upon the downward transition of the Fetch signal, the data will be maintained at memory controller output lines D1 to D4 (which are the Q outputs of the flip-flops) for as long as it takes for the CPU to read the data. In the meantime, the memory controller can be doing other things like refreshing the stored data in the slowly leaking capacitors without worrying about how long it might take for the CPU to actually read the data. Of course, in a real memory controller, there are also address lines to worry about (in this assignment, we assume that the addressing part is already done and the data coming from the memory in M1 to M7 or going to the memory in E1 to E7 are being routed to the right memory bits).
I have a question on Fetch and Store signals: could I assume that only one of them turns on at one time and that both signals are off before either one comes on? I'm thinking of using "OR(Fetch, Store)" as the clock for my flip-flops, but if my assumptions are wrong, I have to change the design.
Yes, you may assume that you will only get one Fetch or Store at any one time, never both together.
I have one more question about assignment #3, do we need to use flip- flops for memory, or D-Latch would be ok? It seems like everything works with D-Latch.
You must use a flip-flop that triggers on the falling edge of the Fetch or Store signals.